As shown in the exploded view in FIG. 1, power modules commonly comprise a semiconductor chip: element E that is capable of generating heat, an electrical insulator I (dielectric substrate) protecting the information inside said semiconductor chip and a cooling system SR that removes heat from the system via a heat exchanger R that is integral with the electrical insulator.
In general, it should be noted that in power electronics, only ceramic substrates mounted on a heat exchanger are currently proposed (for multichip modules that must ensure insulation between chips heat exchanger).
The insulating substrate has two main functions: it may bear the (mainly copper) conductive tracks and also ensure electrical insulation between the semiconductor chips and the cooling system.
An example of a stack frequently employed in the manufacture of power modules more specifically comprises the following components: the semiconductor component (heat source); the solder for mounting the semiconductor component on a substrate; the substrate, which is generally made of a ceramic between two metal plates and is manufactured using various techniques (direct-bonded copper: DBC; active metal brazing: AMB; direct-bonded aluminum: DBA) and allows interconnections (between semiconductors and with the outside) via the top metal tracks and mounting on a base via the bottom metal portion to be achieved. Another solder is also provided in order to mount the substrate on the base, which is generally made of copper Cu and whose role is to spread the thermal flux.
The assembly is then mounted on the radiator using thermal grease.
FIG. 2 diagrammatically shows such a known assembly and the thermal properties of the materials used are given below.
This example of an assembly illustrated in FIG. 1 highlights:
a main heat exchanger R, commonly referred to as a radiator, typically potentially having a thermal conductivity that is greater than 100 W·m−1 K−1 and potentially being made of copper;
a thermal grease Gth with a thickness of 200 μm and a thermal conductivity of the order of 2 W·m−1·K−1;
a mounted copper base M, for spreading heat and forming a secondary heat exchanger, with a thickness of 1000 μm;
a solder B1 of 50 μm and thermal conductivity of the order of 40 W·m−1 K−1;
an insulating substrate I of DBC (direct-bonded copper) type composed of a ceramic plate made of Al2O3 comprising, on its two faces, layers of copper with a thickness that is equal to 300 μm and with a thermal conductivity that is equal to 400 W·m−1 K−1, the ceramic plate having a thickness that is typically of 600 μm and a thermal conductivity that is equal to 20 W·m−1 K−1 (in the case of Al2O3);
a second solder B2 with a thickness that is equal to 50 μm and a thermal conductivity of the order of 40 W·m−1 K−1;
a silicon chip E with a thermal conductivity that is equal to 100 W·m−1 K−1.
This stack has multiple limitations with respect to those applications referred to as “high temperature” applications (a “high temperature” may be due to a high ambient temperature or to the high power density dissipated in the semiconductors) and, in particular, the following drawbacks:
a high thermal resistance initially due to the ceramic, the thermal grease and the nine interfaces between the semiconductor and the cooling fluid that blocks the dissipation of heat and limits the power density of the semiconductors;
poor stability at high temperatures, limited by the operating temperature of the thermal grease and the solders;
limited thermomechanical reliability due to cracking of the ceramic (AlN and Al2O3), cracking in the solder and bowing of the substrate due to asymmetrical thermomechanical stresses imposed by the structure (etched top and full-wafer bottom metal tracks) subsequent to thermal cycle testing.
The use of a metal nanoparticle paste to thermally, mechanically and electrically connect the semiconductor to a substrate has already been described, in particular in U.S. Pat. No. 8,257,795. This replaces the solder between the chip and the metal of the substrate with a sintered silver joint that allows operation at high temperatures and the electrical and thermal properties of the joint to be improved. However, the invention described in this patent does not allow the problems caused by the presence of the ceramic and the presence of the thermal grease to be eliminated.
The adhesion mechanisms between the silver nanoparticle paste and metal and insulating substrates (ceramics and polymers) have also been described in the publication: Nanotechnology 21 (2010), “Adhesion mechanisms of nanoparticle silver to substrate materials: identification”. A thin layer of 2 μm is deposited, then sintered, on polymer (Teflon® and Kapton®) films, subsequent to debonding tests using adhesive tape to assess the adhesion at the interface. The tests are limited to this step, without considering more advanced structures, and relate to very thin layers that are not compatible with power electronics.
The direct printing of a silver nanoparticle paste (with a thickness of less than 2 μm) carried out and sintered at various temperatures on polyimide substrates in order to produce electronic circuits is also known and is described in the article “Sintering and consolidation of silver nanoparticles printed on polyimide substrate films”, published in Macromolecular research 17 (2008). The silver paste on polymer sintering tests are limited to that level.